Simulation of digital logic circuits is performed is using simulation models. The logic function of logic designs containing asynchronous logic boundaries wherein a signal is launched by a circuit element in a first clock domain and captured by a circuit element in a second clock domain, the first and second clock domains specified to be asynchronous to each other, can not be verified by current simulation models. Simply adding delay to current simulation models cannot be relied on to emulate asynchronous logic behavior because, for example, the delays cannot account for such effects as temperature or voltage shifts. Current simulation models also ignore the possibility of transition glitches between the sending of logic pulses. The problem is further complicated when the digital logic circuit includes both synchronous and asynchronous data paths. Current simulation models do not model circuits with both synchronous and asynchronous data paths correctly.
Therefore, there is a need for a simulation methodology for testing and verifying digital logic circuits having asynchronous logic paths.